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february 2012 doc id 022647 rev 1 1/50 1 STA321MP scalable digital microphone processor features 8 digital processing channels each 24-bit ? 6 channels of pdm input ? 2 additional virtual channels >100 db snr and dynamic range digital gain/attenuation +58 db to -100 db in 0.5 db steps soft volume update individual channel and master level control up to 10 independent 32-bit user- programmable biquads (eq) per channel bass/treble tone control pre- and post-eq full 8-channel input mix on all 8 channels dual independent limiters/compressors dynamic range compression or anti-clipping modes individual channel and master soft/hard mute 3 i 2 s data outputs i 2 s data output channel mapping function independent channel volume and dsp bypass channel mapping of any input to any processing channel applications tablets smartphones gaming audio conference sets legacy microphone-equipped devices description the STA321MP is a pdm high-performance multichannel processor with ultra-low quiescent current designed for general-purpose digital microphone applications. the device is fully digital and is comprised of three main sections. the first section is the pdm input interface which can accept up to six serial digital inputs. the second section is a high-quality audio processor allowing flexible channel mixing/muxing and provides up to 10 biquads for general sound equalization and voice enhancement with independent volume control. the last block is the i 2 s output interface which streams out the processed digital audio. the output interface can also be programmed for flexible channel mapping. the device offers some of the most commonly required audio enhancements such as programmable voice tuning and equalization, limiter/compressor for improved voice quality, multiband selection for customizable microphone usage and configurable wind-noise rejection. the embedded digital processor allows offloading the microphone processing from the main cpu or soc, moving it to the device. table 1. device summary order code package packing STA321MPl tqfp64 tube STA321MP vfqfpn56 tube tqfp - 64 10 mm x 10 mm vfqfpn - 56 8 mm x 8 mm www.st.com
contents STA321MP 2/50 doc id 022647 rev 1 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5i 2 c bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.1 data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.3 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.2 multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 application reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2.1 configuration register a (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2.2 configuration register c (0x02) - serial output formats . . . . . . . . . . . . . 23 7.2.3 configuration register e (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2.4 configuration register f (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2.5 configuration register g (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2.6 configuration register h (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STA321MP contents doc id 022647 rev 1 3/50 7.2.7 configuration register i (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2.8 master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2.9 master volume register (0x0a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2.10 channel 1 volume (0x0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2.11 channel 2 volume (0x0c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2.12 channel 3 volume (0x0d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2.13 channel 4 volume (0x0e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2.14 channel 5 volume (0x0f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2.15 channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2.16 channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2.17 channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2.18 channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 30 7.2.19 channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 30 7.2.20 channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 30 7.2.21 channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 31 7.2.22 channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 31 7.2.23 channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 31 7.2.24 channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 31 7.2.25 channel 8 volume trim, mute, bypass (0x1a) . . . . . . . . . . . . . . . . . . . . 31 7.2.26 channel input mapping channels 1 and 2 (0x1b) . . . . . . . . . . . . . . . . . 33 7.2.27 channel input mapping channels 3 and 4 (0x1c) . . . . . . . . . . . . . . . . . 33 7.2.28 channel input mapping channels 5 and 6 (0x1d) . . . . . . . . . . . . . . . . . 33 7.2.29 channel input mapping channels 7 and 8 (0x1e) . . . . . . . . . . . . . . . . . 33 7.2.30 biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 34 7.2.31 mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 35 7.2.32 eq bypass (0x2a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2.33 tone control bypass (0x2b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2.34 tone control (0x2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.35 channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.36 channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.37 channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.38 channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2.39 channel i 2 s output mapping channels 1 and 2 (0x37) . . . . . . . . . . . . . 37 7.2.40 channel i 2 s output mapping channels 3 and 4 (0x38) . . . . . . . . . . . . . 37 7.2.41 channel i 2 s output mapping channels 5 and 6 (0x39) . . . . . . . . . . . . . 37 7.2.42 channel i 2 s output mapping channels 7 and 8 (0x3a) . . . . . . . . . . . . . 38 7.2.43 coefficient address register 1 (0x3b) . . . . . . . . . . . . . . . . . . . . . . . . . . 38
contents STA321MP 4/50 doc id 022647 rev 1 7.2.44 coefficient address register 2 (0x3c) . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2.45 coefficient b1 data register, bits 23:16 (0x3d) . . . . . . . . . . . . . . . . . . . . 38 7.2.46 coefficient b1 data register, bits 15:8 (0x3e) . . . . . . . . . . . . . . . . . . . . . 39 7.2.47 coefficient b1 data register, bits 7:0 (0x3f) . . . . . . . . . . . . . . . . . . . . . . 39 7.2.48 coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 39 7.2.49 coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 39 7.2.50 coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 39 7.2.51 coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 39 7.2.52 coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 39 7.2.53 coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 40 7.2.54 coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 40 7.2.55 coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 40 7.2.56 coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 40 7.2.57 coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 40 7.2.58 coefficient b0 data register, bits 15:8 (0x4a) . . . . . . . . . . . . . . . . . . . . . 40 7.2.59 coefficient b0 data register, bits 7:0 (0x4b) . . . . . . . . . . . . . . . . . . . . . . 40 7.2.60 coefficient write control register (0x4c) . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.3 reading a coefficient from ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.4 reading a set of coefficients from ram . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.5 writing a single coefficient to ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.6 writing a set of coefficients to ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8 equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1 post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2 variable max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.2.1 mpcc1-2 (0x4d, 0x4e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3 variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3.1 dcc1-2 (0x4f, 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.4 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 tqfp64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2 vfqfpn56 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STA321MP list of tables doc id 022647 rev 1 5/50 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description: tqfp-64 (STA321MPl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. pin description: vfqfpn-56 (STA321MP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. general interface electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 table 8. dc electrical characteristics: 3.3-v buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 table 9. register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 10. ram block for biquads, mixing, and bass management. . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 11. vfqfpn56 (8 x 8 x 0.9 mm) package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 12. exposed pad variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
list of figures STA321MP 6/50 doc id 022647 rev 1 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. channel signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. reference schematic for STA321MP-based application . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. channel mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 9. tqfp64 (10 x 10 x 1.4 mm) mechanical data and package dimensions . . . . . . . . . . . . . . 46 figure 10. vfqfpn56 (8 x 8 x 0.9 mm) package mechanical outline . . . . . . . . . . . . . . . . . . . . . . . . . 47
STA321MP block diagram doc id 022647 rev 1 7/50 1 block diagram figure 1. block diagram figure 2. channel signal flow ffx am045 3 27v1 am045 3 2 8 v1
pin connections STA321MP 8/50 doc id 022647 rev 1 2 pin connections figure 3. pin connections (top view) am045 3 29v1 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 2 3 4 5 6 7 8 10 10 11 12 pdm_clk gnd vdd3 gnd pdmin_6 pdmin_5 pdmin_4 pdmin_3 pdmin_2 pdmin_1 vdd3 gnd 13 14 pllb reset 17 18 19 20 21 22 23 24 25 26 27 28 out8a sda scl xti filter_pll vdda gnda vdd3 ckout gnd vdd3 out8b out7a out7b 15 16 out1b vdd3 out2a out2b gnd vdd3 out3a out3b out4a out4b out5a out5b gnd out6a out6b pwdn sdo_56 gnd vdd3 sdo_12 lrcko sdo_34 biko gnd vdd3 out1a eapd sdo_78 vfqfpn-56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 48 47 46 45 44 43 42 41 40 39 38 37 36 35 64 63 62 61 60 59 58 57 56 55 54 53 52 51 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pdm_clk nc gnd vdd3 gnd nc pdmin_6 pdmin_5 pdmin_4 pdmin_3 pdmin_2 pdmin_1 vdd3 gnd out2a vdd3 out2b nc gnd vdd3 out3a out3b out4a out4b out5a out5b nc gnd nc out8a sda scl xti filter_pll vdda gnda vdd3 ckout nc gnd vdd3 out8b pwdn eapd sdo_78 sdo_56 nc gnd vdd3 sdo_12 lrcko sdo_34 biko nc gnd vdd3 15 16 pllb reset 31 32 50 49 34 33 out7a out7b out6a out6b out1b out1a tqfp-64
STA321MP pin connections doc id 022647 rev 1 9/50 table 2. pin description: tqfp-64 (STA321MPl) pin number type name description 1 5-v tolerant ttl input buffer pdm_clk pdm i/f clk 6 5-v tolerant ttl input buffer pdmin_6 pdm input channel 6 7 5-v tolerant ttl input buffer pdmin_5 pdm input channel 5 8 5-v tolerant ttl input buffer pdmin_4 pdm input channel 4 9 5-v tolerant ttl input buffer pdmin_3 pdm input channel 3 10 5-v tolerant ttl input buffer pdmin_2 pdm input channel 2 11 5-v tolerant ttl input buffer pdmin_1 pdm input channel 1 15 5-v tolerant ttl schmitt trigger input buffer reset global reset 16 cmos input buffer with pull-down pllb bypass phase-locked loop 18 bidirectional buffer: 5-v tolerant ttl schmitt trigger input; 3.3-v capable 2 ma slew-rate controlled output sda serial data (i 2 c) 19 5-v tolerant ttl schmitt trigger input buffer scl serial clock (i 2 c) 20 5-v tolerant ttl schmitt trigger input buff er xti crystal oscillator input (clock input) 21 analog pad filter_pll pll filter 22 3.3-v analog supply voltage vdda pll supply 23 analog ground gnda pll ground 25 3.3-v capable ttl tristate 4 ma output buffer ckout clock output 29 3.3-v capable ttl 2 ma output buffer out8b pwm channel 8 output b 30 3.3-v capable ttl 2 ma output buffer out8a pwm channel 8 output a 31 3.3-v capable ttl 2 ma output buffer out7b pwm channel 7 output b 32 3.3-v capable ttl 2 ma output buffer out7a pwm channel 7 output a 33 3.3-v capable ttl 2 ma output buffer out6b pwm channel 6 output b 34 3.3-v capable ttl 2 ma output buffer out6a pwm channel 6 output a 38 3.3-v capable ttl 2 ma output buffer out5b pwm channel 5 output b 39 3.3-v capable ttl 2 ma output buffer out5a pwm channel 5 output a 40 3.3-v capable ttl 2 ma output buffer out4b pwm channel 4 output b 41 3.3-v capable ttl 2 ma output buffer out4a pwm channel 4 output a 42 3.3-v capable ttl 2 ma output buffer out3b pwm channel 3 output b 43 3.3-v capable ttl 2 ma output buffer out3a pwm channel 3 output a 47 3.3-v capable ttl 2 ma output buffer out2b pwm channel 2 output b 48 3.3-v capable ttl 2 ma output buffer out2a pwm channel 2 output a 49 3.3-v capable ttl 2 ma output buffer out1b pwm channel 1 output b 50 3.3-v capable ttl 2 ma output buffer out1a pwm channel 1 output a
pin connections STA321MP 10/50 doc id 022647 rev 1 51 3.3-v capable ttl 4 ma outpu t buffer eapd ext. amp power-down 55 3.3-v capable ttl 2 ma output buffer bicko output serial clock 56 3.3-v capable ttl 2 ma output bu ffer lrcko output left/right clock 57 3.3-v capable ttl 2 ma output buffer sd o_12 output serial data channels 1 & 2 58 3.3-v capable ttl 2 ma output buffer sd o_34 output serial data channels 3 & 4 62 3.3-v capable ttl 2 ma output buffer sd o_56 output serial data channels 5 & 6 63 3.3-v capable ttl 2 ma output buffer sd o_78 output serial data channels 7 & 8 64 5-v tolerant ttl schmitt trigger input buffer pwdn device power-down 3,12,24, 28,35, 44,52,59 3.3-v digital supply voltage vdd3 3.3-v supply 2,4,13, 27,36, 45,53,60 digital ground gnd ground 14,17,26, 37, 46, 54,61,63 nc not connected table 2. pin description: tqfp-64 (STA321MPl) (continued) pin number type name description table 3. pin description: vfqfpn-56 (STA321MP) pin number type name description 1 5-v tolerant ttl input buffer pdm_clk pdm i/f clk 5 5-v tolerant ttl input buffer pdmin_6 pdm input channel 6 6 5-v tolerant ttl input buffer pdmin_5 pdm input channel 5 7 5-v tolerant ttl input buffer pdmin_4 pdm input channel 4 8 5-v tolerant ttl input buffer pdmin_3 pdm input channel 3 9 5-v tolerant ttl input buffer pdmin_2 pdm input channel 2 10 5-v tolerant ttl input buffer pdmin_1 pdm input channel 1 13 5-v tolerant ttl schmitt trigge r input buffer reset global reset 14 cmos input buffer with pull-down pllb bypass phase-locked loop 15 bidirectional buffer: 5-v tolerant ttl schmitt trigger input; 3.3-v capable 2 ma slew-rate controlled output sda serial data (i 2 c) 16 5-v tolerant ttl schmitt trigger input buffer scl serial clock (i 2 c) 17 5-v tolerant ttl schmitt trigger input buff er xti crystal oscillator input (clock input) 18 analog pad filter_pll pll filter 19 3.3-v analog supply voltage vdda pll supply
STA321MP pin connections doc id 022647 rev 1 11/50 20 analog ground gnda pll ground 22 3.3-v capable ttl tristate 4 ma output buffer ckout clock output 25 3.3-v capable ttl 2 ma output buffer out8b pwm channel 8 output b 26 3.3-v capable ttl 2 ma output buffer out8a pwm channel 8 output a 27 3.3-v capable ttl 2 ma output buffer out7b pwm channel 7 output b 28 3.3-v capable ttl 2 ma output buffer out7a pwm channel 7 output a 29 3.3-v capable ttl 2 ma output buffer out6b pwm channel 6 output b 30 3.3-v capable ttl 2 ma output buffer out6a pwm channel 6 output a 33 3.3-v capable ttl 2 ma output buffer out5b pwm channel 5 output b 34 3.3-v capable ttl 2 ma output buffer out5a pwm channel 5 output a 35 3.3-v capable ttl 2 ma output buffer out4b pwm channel 4 output b 36 3.3-v capable ttl 2 ma output buffer out4a pwm channel 4 output a 37 3.3-v capable ttl 2 ma output buffer out3b pwm channel 3 output b 38 3.3-v capable ttl 2 ma output buffer out3a pwm channel 3 output a 41 3.3-v capable ttl 2 ma output buffer out2b pwm channel 2 output b 42 3.3-v capable ttl 2 ma output buffer out2a pwm channel 2 output a 43 3.3-v capable ttl 2 ma output buffer out1b pwm channel 1 output b 44 3.3-v capable ttl 2 ma output buffer out1a pwm channel 1 output a 45 3.3-v capable ttl 4 ma output buffer eapd ext. amp power-down 48 3.3-v capable ttl 2 ma output buffer bicko output serial clock 49 3.3-v capable ttl 2 ma output buffer lrcko output left/right clock 50 3.3-v capable ttl 2 ma output buffer sdo_12 output serial data channels 1 & 2 51 3.3-v capable ttl 2 ma output buffer sdo_34 output serial data channels 3 & 4 54 3.3-v capable ttl 2 ma output buffer sdo_56 output serial data channels 5 & 6 55 3.3-v capable ttl 2 ma output buffer sdo_78 output serial data channels 7 & 8 56 5-v tolerant ttl schmitt trigger input buffer pwdn device power-down 3,11,21, 24,31, 39,46,52 3.3-v digital supply voltage vdd3 3.3-v supply 2,4,12, 23,32, 40,47,53 digital ground gnd ground table 3. pin description: vfqfpn-56 (STA321MP) (continued) pin number type name description
electrical specifications STA321MP 12/50 doc id 022647 rev 1 3 electrical specifications 3.1 absolute maximum ratings 3.2 thermal data 3.3 recommended operating conditions table 4. absolute maximum ratings symbol parameter min typ max unit v dd 3.3-v i/o power supply -0.5 4 v v dda 3.3-v logic power supply -0.5 4 v v i voltage on input pins -0.5 vdd + 0.5 v v o voltage on output pins -0.5 vdd + 0.3 v t stg storage temperature -40 150 c t amb ambient operating temperature -40 90 c table 5. thermal data symbol parameter min typ max unit r thj-case thermal resistance, junction-case (thermal pad) STA321MP 1.5 c/w table 6. recommended operating conditions symbol parameter min typ max unit v dd i/o power supply 3.0 3.6 v v dda logic power supply 3.0 3.6 v t j operating junction temperature -40 125 c
STA321MP electrical specifications doc id 022647 rev 1 13/50 3.4 electrical specifications the following specifications are valid for v dd = 3.3 v 0.3 v, v dda = 3.3 v 0.3 v and tamb = 0 to 70 c, unless otherwise stated table 7. general interface electrical specifications symbol parameter conditions min typ max unit i il low-level input no pull-up v i = 0 v 1 (1) 1. the leakage currents are generally very small, < 1 na. the values given here are maximum after an electrostatic stress on the pin. a i ih high-level input no pull-down v i = v dd 2 a i oz tristate output leakage without pull-up/down v i = v dd 2 a v esd electrostatic protection (human body model) leakage < 1 a2000v table 8. dc electrical characteristics: 3.3-v buffers symbol parameter conditions min typ max unit v il low-level input voltage 0.8 v v ih high-level input voltage 2.0 v v ilhyst low-level threshold input falling 0.8 1.35 v v ihhyst high-level threshold input rising 1.3 2.0 v v hyst schmitt trigger hysteresis 0.3 0.8 v v ol low-level output i oi = 100 a 0.2 v v oh high-level output i oh = -100 a vdd- 0.2 v i oh = -2 ma 2.4 v
pin description STA321MP 14/50 doc id 022647 rev 1 4 pin description pdm interface clock (pdm_clk) the clock to the pdm interface is provided on this pin and will be used by the device to sample the digital microphone data. this clock must be used to clock both the interface and the microphones. the clock frequency must not exceed the upper limit of the microphone?s specific clock frequency (please refer to th e datasheet of the specific microphone used). pdm input channels (pdmin_1/6) audio information enters the device through the pdm input channels. these input pins receive the digital output signal from the microphones. reset driving this pin low turns off the outputs and returns all settings to their defaults. i 2 c bus the sda and scl pins op erate per the phillips i 2 c specification. see section 5: i 2 c bus operation . phase-locked loop (pll) the phase-locked loop section provides the system timing signals and ckout. clock output (ckout) system synchronization and master clocks are provided by ckout. this clock can be conveniently divided and then used to cloc k both the pdm interface and the microphones. please refer to figure 6. pwm outputs (out1 through out8) the pwm outputs provide the input signal for the power devices. serial data out (sdo_12, sdo_34, sdo_56, sdo_78) these are the outputs for audio information. six different formats are available including i 2 s, left- or right-justified, lsb or msb first, with word widths of 16, 18, 20 and 24 bits. device power-down (pwdn) pulling pwdn low begins the power-down sequence which puts the STA321MP into a low-power state. eapd (pin 45 of the vfqfn- 56 or pin 51 of the tqfp-64) goes low approximately 30 ms later.
STA321MP i 2 c bus operation doc id 022647 rev 1 15/50 5 i 2 c bus operation the STA321MP supports the i 2 c protocol via the input ports scl and sda_in (master to slave) and the output port sda_out (slave to master). this protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. the STA321MP is always a slave device in all of its communications. 5.1 communication protocol 5.1.1 data transition or change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high is used to identify a start or stop condition. 5.1.2 start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. 5.1.3 stop condition stop is identified by a low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communication between STA321MP and the bus master. 5.1.4 data input during the data input the STA321MP samples the sda signal on the rising edge of clock scl. for correct device operation the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. 5.2 device addressing to start communication between the master and the omega ffx core, the master must initiate with a start condition. following this , the master sends 8 bits to the sda line (msb first) corresponding to the device select address and read or write mode. the 7 most significant bits are the device address identifiers, corresponding to the i 2 c bus definition. in the STA321MP the i 2 c interface has two device addresses depending on the sa port configuration, 0x40 or 0100000x when sa = 0, and 0x42 or 0100001x when sa = 1. the 8 th bit (lsb) identifies a read or write operation rw, this bit is set to 1 in read mode and 0 for write mode. after a start condition the STA321MP identifies on the bus the device
i 2 c bus operation STA321MP 16/50 doc id 022647 rev 1 address and if a match is found, it acknowledges the identification on sda bus during the 9 th -bit time. the byte following the device identification byte is the internal space address. 5.3 write operation following the start condition the master sends a device select code with the rw bit set to 0. the STA321MP acknowledges this and then waits for the byte of internal address. after receiving the internal byte address the STA321MP again responds with an acknowledgement. 5.3.1 byte write in the byte write mode the master sends one data byte, which is acknowledged by the ffx core. the master then terminates the transfer by generating a stop condition. 5.3.2 multi-byte write the multi-byte write modes can start from any internal address. the master generating a stop condition terminates the transfer. figure 4. write mode sequence figure 5. read mode sequence dev-addr ack start rw sub-addr ack data in a ck stop byte write dev-addr ack start rw sub-addr ack data in a ck stop multibyte write data in a ck am045 33 0v1 dev-addr ack start rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr a ck stop random address read data no a ck w r t r a t s dev-addr ack start data ack data ack stop sequential current read data no a ck dev-addr ack start rw sub-addr ack dev-addr a ck sequential random read data a ck w r t r a t s data a ck no a ck stop data rw= high am045 33 1v1
STA321MP application reference schematic doc id 022647 rev 1 17/50 6 application reference schematic figure 6. reference schematic for STA321MP-based application figure 7. application circuit pdm_clk xti sda reset pll_bypass pdm_in1 pdm_in2 pdm_in3 pdm_in4 pdm_in5 pdm_in6 scl filter_pll i2s receiver/ processor or audio precision 100nf 3.3v 100pf 1nf 3.3k outxb vdd3 gnd bicko lrcko sdo_12 sdo_34 sdo_56 ck data lr gnd vdd ck data lr gnd vdd ck data lr gnd vdd ck data lr gnd vdd ck data lr gnd vdd ck data lr gnd vdd 3.3v digital microphones ckout dual flip/flop ck divider outxa analog output interface external clock 11.2896 mhz control interface am045 33 2v1
registers STA321MP 18/50 doc id 022647 rev 1 7 registers 7.1 register summary table 9. register summary addr name d7 d6 d5 d4 d3 d2 d1 d0 configuration 0x00 confa cos1 cos0 dspb ir1 ir0 mcs2 mcs1 mcs0 0x01 confb saifb sai3 sai2 sai1 sai0 0x02 confc saofb sao3 sao2 sao1 sao0 0x03 confd mpc csz4 csz3 csz2 csz1 csz0 om1 om0 0x04 confe c8bo c7bo c6bo c5bo c4bo c3bo c2bo c1bo 0x05 conff pwms2 pwms1 pwms0 bql psl demp drc hpb 0x06 confg mpcv dccv hpe am2e ame cod sid pwmd 0x07 confh ecle ldte bcle ide zde sve zce nsbw 0x08 confi eapd psce volume control 0x09 mmute mmute 0x0a mvol mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 0x0b c1vol c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 0x0c c2vol c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 0x0d c3vol c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 0x0e c4vol c4v7 c4v6 c4v5 c4v4 c4v3 c4v2 c4v1 c4v0 0x0f c5vol c5v7 c5v6 c5v5 c5v4 c5v3 c5v2 c5v1 c5v0 0x10 c6vol c6v7 c6v6 c6v5 c6v4 c6v3 c6v2 c6v1 c6v0 0x11 c7vol c7v7 c7v6 c7v5 c7v4 c7v3 c7v2 c7v1 c7v0 0x12 c8vol c8v7 c8v6 c8v5 c8v4 c8v3 c8v2 c8v1 c8v0 0x13 c1vtmb c1m c1vbp c1vt4 c1vt3 c1vt2 c1vt1 c1vt0 0x14 c2vtmb c2m c2vbp c2vt4 c2vt3 c2vt2 c2vt1 c2vt0 0x15 c3vtmb c3m c3vbp c3vt4 c3vt3 c3vt2 c3vt1 c3vt0 0x16 c4vtmb c4m c4vbp c4vt4 c4vt3 c4vt2 c4vt1 c4vt0 0x17 c5vtmb c5m c5vbp c5vt4 c5vt3 c5vt2 c5vt1 c5vt0 0x18 c6vtmb c6m c6vbp c6vt4 c6vt3 c6vt2 c6vt1 c6vt0 0x19 c7vtmb c7m c7vbp c7vt4 c7vt3 c7vt2 c7vt1 c7vt0 0x1a c8vtmb c8m c8vbp c8vt4 c8vt3 c8vt2 c8vt1 c8vt0
STA321MP registers doc id 022647 rev 1 19/50 input mapping 0x1b c12im c2im2 c2im1 c2im0 c1im2 c1im1 c1im0 0x1c c34im c4im2 c4im1 c4im0 c3im2 c3im1 c3im0 0x1d c56im c6im2 c6im1 c6im0 c5im2 c5im1 c5im0 0x1e c78im c8im2 c8im1 c8im0 c7im2 c7im1 c7im0 processing loop 0x28 bqlp c8blp c7blp c6blp c5blp c4blp c3blp c2blp c1blp 0x29 mxlp c8mxlp c7mxlp c6mxlp c5mxlp c4mxlp c3mxlp c2mxlp c1mxlp processing bypass 0x2a eqbp c8eqbp c7eqbp c6eqbp c5eqbp c4eqbp c3eqbp c2eqbp c1eqbp 0x2b tonebp c8tcb c7tcb c6tcb c5tcb c4tcb c3tcb c2tcb c1tcb tone control 0x2c tone ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 pwm output timing 0x33 c12ot c2ot2 c2ot1 c2ot0 c1ot2 c1ot1 c1ot0 0x34 c34ot c4ot2 c4ot1 c4ot0 c3ot2 c3ot1 c3ot0 0x35 c56ot c6ot2 c6ot1 c6ot0 c5ot2 c5ot1 c5ot0 0x36 c78ot c8ot2 c8ot1 c8ot0 c7ot2 c7ot1 c7ot0 i 2 s output channel mapping 0x37 c12om c2om2 c2om1 c2om0 c1om2 c1om1 c1om0 0x38 c34om c4om2 c4om1 c4om0 c3om2 c3om1 c3om0 0x39 c56om c6om2 c6om1 c6om0 c5om2 c5om1 c5om0 0x3a c78om c8om2 c8om1 c8om0 c7om2 c7om1 c7om0 user-defined coefficient ram 0x3b cfaddr1 cfa9 cfa8 0x3c cfaddr2 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 0x3d b1cf1 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 0x3e b1cf2 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 0x3f b1cf3 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 0x40 b2cf1 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 0x41 b2cf2 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 0x42 b2cf3 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 0x43 a1cf1 c3b23 c3b22 c3b21 c3b20 c3b19 c3b18 c3b17 c3b16 table 9. register summary (continued) addr name d7 d6 d5 d4 d3 d2 d1 d0
registers STA321MP 20/50 doc id 022647 rev 1 0x44 a1cf2 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 0x45 a1cf3 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 0x46 a2cf1 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 0x47 a2cf2 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 0x48 a2cf3 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 0x49 b0cf1 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 0x4a b0cf2 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 0x4b b0cf3 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 0x4c cfud wa w1 0x4d mpcc1 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 0x4e mpcc2 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 0x4f dcc1 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 0x50 dcc2 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 0x51 psc1 rcv11 rcv10 rcv9 rcv8 rcv7 rcv6 rcv5 rcv4 0x52 psc2 rcv3 rcv2 rcv1 rcv0 cnv11 cnv10 cnv9 cnv8 0x53 psc3 cnv7 cnv6 cnv5 cnv4 cnv3 cnv2 cnv1 cnv0 table 9. register summary (continued) addr name d7 d6 d5 d4 d3 d2 d1 d0
STA321MP registers doc id 022647 rev 1 21/50 7.2 register description 7.2.1 configuration register a (0x00) the STA321MP supports a sampling rate of 2.8224 mhz. therefore the internal clock is: 90.3168 mhz for the respective sampling frequency the external clock frequency provided to the xti pin must be a multiple of the input sampling frequency (fs). the relationship between the input clock and the input sampling rate is determined by both the mcsn and the irn (input rate) register bits. the mcsn bits determine the pll factor generating the internal clock and the irn bits determine the oversampling ratio used internally. interpolation ratio select the STA321MP has variable interpolation (oversampling) settings such that internal processing and ffx output rates remain consis tent. the first processing block interpolates by either 4 times, 2 times, or 1 time (pass-through). the oversampling ratio of this interpolation is determined by the ir bits. i d7 d6 d5 d4 d3 d2 d1 d0 cos1 cos0 dspb ir1 ir0 mcs2 mcs1 mcs0 10000011 bit rw rst name description 0rw1 mcs0 master clock select: sele cts the ratio between the input sampling frequency (pdm i/fclk) and the input clock(xti). 1rw1 mcs1 2rw0 mcs2 input sampling rate fs (khz) ir mcs[2:0] 1xx 011 010 001 000 pdm i/f 2822.4 11 2 * fs 4 * fs 6 * fs 8 * fs 10 * fs bit rw rst name description 3 rw 0 ir0 interpolation ratio se lect: selects the internal interpolation ratio based on the input sampling frequency 4rw 0 ir1 ir[1,0] input sampling rate fs (khz) 1 st stage interpolation ratio 11 2822.4 pdm clk to 176.4 khz conversion
registers STA321MP 22/50 doc id 022647 rev 1 setting the dspb bit bypasses the bi quad function of the ffx core. application example: external clock: xti=11.2896 mhz cos[1,0] = 10: ckout= 90.3168 mhz / 8 = 11.2896 mhz external dual flip flop pdm i/f = ckout/4 = 2.8224 mhz, also provided to the microphones mcs[2:0]= 011: xti /fs = 4 bit rw rst name description 0 rw 0 dspb dsp bypass bit: 0: normal operation 1: bypass of biquad and bass/treble functions cos[1,0] ckout frequency 00 pll output 01 pll output / 4 10 pll output / 8 11 pll output / 16
STA321MP registers doc id 022647 rev 1 23/50 7.2.2 configuration register c (0x02) - serial output formats the STA321MP features a serial audio output interface that consists of 8 channels. the serial audio output acts as a master with an output sampling frequency of 176.4 khz. the output serial format can be selected independently from the input format and is done via the sao and saofb bits. d7 d6 d5 d4 d3 d2 d1 d0 saofb sao3 sao2 saio sao0 00000 bit rw rst name description 0rw 0 sao0 serial audio output interface format: determines the interface format of the output serial digital audio interface. 1rw 0 sao1 2rw 0 sao2 3rw 0 sao3 bit rw rst name description 4rw 0 saofb determines msb or lsb first for all sao formats: 0: msb first 1: lsb first bicki = bicko sao[3:0] interface data format 32 * fs 0111 i 2 s data 1111 left/right-justified 16-bit data 48 * fs 1110 i 2 s data 0001 left-justified data 1010 right-justified 24-bit data 1011 right-justified 20-bit data 1100 right-justified 18-bit data 1101 right-justified 16-bit data 64 * fs 0000 i 2 s data 0001 left-justified data 0010 right-justified 24-bit data 0011 right-justified 20-bit data 0100 right-justified 18-bit data 0101 right-justified 16-bit data
registers STA321MP 24/50 doc id 022647 rev 1 7.2.3 configuration register e (0x04) each individual channel output can be set to output a binary pwm stream. in this mode output a of a channel will be considered the positive output and output b is the negative inverse. 7.2.4 configurati on register f (0x05) the STA321MP features an internal digital high-pass filter for the purpose of ac coupling. the purpose of this filter is to prevent dc signals from passing through an ffx amplifier. dc signals can cause speaker damage. if hpb = 1, then the filter that the high-pass filter utilizes is made available as user- programmable biquad#1. both limiters can be used in one of two ways, anti-clipping or dynamic range compression. when used in anti-clipping mode, the limiter threshold values are constant and dependent on the limiter settings. d7 d6 d5 d4 d3 d2 d1 d0 c8bo c7bo c6bo c5bo c4bo c3bo c2bo c1bo 00000000 bit rw rst name description 0rw 0 c1bo channels 1, 2, 3, 4, 5, 6, 7, and 8 binary output mode enable bits. a setting of 0 indicates ordinary ffx tristate output. a setting of 1 indicates binary output mode. 1rw 0 c2bo 2rw 0 c3bo 3rw 0 c4bo 4rw 0 c5bo 5rw 0 c6bo 6rw 0 c7bo 7rw 0 c8bo d7 d6 d5 d4 d3 d2 d1 d0 pwms2 pwms1 pwms0 bql psl demp drc hpb 00000000 bit rw rst name description 0rw 0 hpb high-pass filter bypass bit: a setting of 1 bypasses the internal ac coupling digital high-pass filter bit rw rst name description 1 rw 0 drc dynamic range compression/anti-clipping 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode
STA321MP registers doc id 022647 rev 1 25/50 in dynamic range compression mode the limiter threshold values vary with the volume settings, allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of th e volume level. by setting this bit to one, de-emphasis will be implemented on all channels. when this is used it takes the place of biquad #7 in each channel and any coefficients using biquad #1 will be ignored. the dspb (d sp bypass) bit must be set to 0 for de-emphasis to function. post-scale functionality can be used for power-supply error correction. for multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and in order to update the values faster. for ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient ram space by setting the bql bit to 1. therefore, any eq updates only have to be performed once. bit rw rst name description 2rw 0 demp de-emphasis: 0: no de-emphasis 1: de-emphasis bit rw rst name description 3 rw 0 psl post-scale link: 0: each channel uses individual post-scale values 1: each channel uses channel 1 post-scale values bit rw rst name description 4rw 0 bql biquad link: 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values bit rw rst name description 7:5 rw 00 pwms[2:0] pwm speed selection pwms[1:0] pwm output speed 000 normal speed (384 khz) (all channels) 001 half-speed (192 khz) (all channels) 010 double-speed (768 khz) (all channels) 011 normal speed (channels 1-6), double-speed (channels 7-8) 100 odd speed (341.3 khz) (all channels)
registers STA321MP 26/50 doc id 022647 rev 1 7.2.5 configuration register g (0x06) the STA321MP features an ffx processing m ode that minimizes the amount of noise generated in the frequency range of am radio. this mode is intended for use when ffx is operating in a device with an active am tuner. the snr of the ffx processing is reduced to ~83 db in this mode, which is still gr eater than the snr of am radio. the STA321MP features two ffx processing modes that minimize the amount of noise generated in the frequency range of am radio. this second mode is intended for use when ffx is operating in a device with an active am tuner. this mode eliminates the noise- shaper. channels 7 and 8 can be configured to be processed and output in such a manner that headphones can be driven using an appropriate output device. this signal is a differential 3-wire drive called ffx headphone. d7 d6 d5 d4 d3 d2 d1 d0 mpcv dccv hpe am2e ame cod sid pwmd 00000000 bit rw rst name description 0rw0 pwmd pwm output disable: 0: pwm output normal 1: no pwm output 1rw0 sid serial interface (i 2 s out) disable: 0: i 2 s output normal 1: no i 2 s output 2rw0 cod clock output disable: 0: clock output normal 1: no clock output bit rw rst name description 3rw 0 ame am mode enable: 0: normal ffx operation 1: am reduction mode ffx operation bit rw rst name description 4rw 0 am2e am2 mode enable: 0: normal ffx operation 1: am2 reduction mode ffx operation bit rw rst name description 5rw 0 hpe ffx headphone enable: 0: channels 7 and 8 normal ffx operation 1: channels 7 and 8 headphone operation
STA321MP registers doc id 022647 rev 1 27/50 7.2.6 configuration register h (0x07) the zce bit enables zero-crossing volume adjustments. when volume is adjusted on digital zero-crossings, no clicks will be audible. setting the zde bit enables the zero-detect automatic mute. the zero-detect circuit looks at the input data to each processing channel afte r the channel-mapping block. if any channel receives 2048 consecutive zero value samples (regardless of fs), then that individual channel is muted if this function is enabled. bit rw rst name description 6 rw 0 dccv distortion compensation variable enable : 0: uses preset dc coefficient 1: uses dcc coefficient bit rw rst name description 7rw 0 mpcv max power correction variable: 0: use standard mpc coefficient 1: use mpcc bits for mpc coefficient d7 d6 d5 d4 d3 d2 d1 d0 ecle ldte bcle ide zde sve zce nsbw 01111110 bit rw rst name description 0 rw 0 nsbw noise-shaper bandwidth selection: 1: 3 rd order ns 0: 4 th order ns bit rw rst name description 1rw1 zce zero-crossing volume enable: 1: volume adjustments will only occur at digital zero- crossings 0: volume adjustments will occur immediately bit rw rst name description 2rw1 sve soft volume enable: 1: volume adjustments use soft volume 0: volume adjustments occur immediately bit rw rst name description 3rw1 zde zero-detect mute enable: setting of 1 enables the automatic zero-detect mute
registers STA321MP 28/50 doc id 022647 rev 1 setting the ide bit enables this function, which looks at the input i 2 s data and will automatically mute if the signals are perceived as invalid. the bcle bit detects loss of input mclk in binary mode and will output 50% duty cycle. the ldte bit actively prevents double triggering of lrclk. the ecle bit controls the device power down signal (eapd) on clock loss detection. this function is enabled by default. it is strong ly recommended to avoid spurious noise during the on-off sequence. the STA321MP has the ecle bit set to 0. 7.2.7 configuration register i (0x08) this feature utilizes an adc on sdi78 that pr ovides power supply ripple information for correction. regist ers psc1, psc2, psc3 are utilized in this mode. bit rw rst name description 4rw 1 ide invalid input detect mute enable: 1: enable the automatic invalid input detect mute bit rw rst name description 5 rw 1 bcle binary output mode clock loss detection enable bit rw rst name description 6 rw 1 ldte lrclk double trigger protection enable bit rw rst name description 7 rw 1 ecle auto eapd on clock loss d7 d6 d5 d4 d3 d2 d1 d0 eapd psce 0 0 bit rw rst name description 0 rw 0 psce power supply ripple correction enable: 0: normal operation 1: pscorrect operation bit rw rst name description 7 rw 0 eapd external amplifier power down: 0: external power stage power-down active 1: normal operation
STA321MP registers doc id 022647 rev 1 29/50 7.2.8 master mute register (0x09) 7.2.9 master volume register (0x0a) note: the value of the volume derived from mvol is dependent on the amv automode volume settings. 7.2.10 channel 1 volume (0x0b) 7.2.11 channel 2 volume (0x0c) 7.2.12 channel 3 volume (0x0d) 7.2.13 channel 4 volume (0x0e) d7 d6 d5 d4 d3 d2 d1 d0 mmute 0 d7 d6 d5 d4 d3 d2 d1 d0 mv7 mv6 mv5 mv4 mv3 mv2 mv1 mv0 11111111 d7 d6 d5 d4 d3 d2 d1 d0 c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c4v7 c4v6 c4v5 c4v4 c4v3 c4v2 c4v1 c4v0 01100000
registers STA321MP 30/50 doc id 022647 rev 1 7.2.14 channel 5 volume (0x0f) 7.2.15 channel 6 volume (0x10) 7.2.16 channel 7 volume (0x11) 7.2.17 channel 8 volume (0x12) 7.2.18 channel 1 volume trim, mute, bypass (0x13) 7.2.19 channel 2 volume trim, mute, bypass (0x14) 7.2.20 channel 3 volume trim, mute, bypass (0x15) d7 d6 d5 d4 d3 d2 d1 d0 c5v7 c5v6 c5v5 c5v4 c5v3 c5v2 c5v1 c5v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c6v7 c6v6 c6v5 c6v4 c6v3 c6v2 c6v1 c6v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c7v7 c7v6 c7v5 c7v4 c7v3 c7v2 c7v1 c7v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c8v7 c8v6 c8v5 c8v4 c8v3 c8v2 c8v1 c8v0 01100000 d7 d6 d5 d4 d3 d2 d1 d0 c1m c1vbp c1vt4 c1vt3 c1vt2 c1vt1 c1vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c2m c2vbp c2vt4 c2vt3 c2vt2 c2vt1 c2vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c3m c3vbp c3vt4 c3vt3 c3vt2 c3vt1 c3vt0 00010000
STA321MP registers doc id 022647 rev 1 31/50 7.2.21 channel 4 volume trim, mute, bypass (0x16) 7.2.22 channel 5 volume trim, mute, bypass (0x17) 7.2.23 channel 6 volume trim, mute, bypass (0x18) 7.2.24 channel 7 volume trim, mute, bypass (0x19) 7.2.25 channel 8 volume trim, mute, bypass (0x1a) the volume structure of the STA321MP consists of individual volume registers for each channel and a master volume register that provides an offset to each channel?s volume setting. there is also an additional offset for each channel called the channel volume trim. the individual channel volumes are adjustable in 0.5 db steps from +48 db to -78 db. as an example, if c5v = 0xxx or +xxx db and mv = 0xxx or -xx db, then the total gain for channel 5 = xx db. the channel volume trim is adjustable independently on each channel from -10 db to +10 db in 1 db steps. the master mute when set to 1 will mute all channels at once, whereas the individual channel mutes (c nm) will mute only that channel. both the master mute and the channel mutes provide a "soft mute" with the volume ramping down to mute in 8192 samples from the maximum volume setting at the internal processing rate (~192 khz). a "hard mute" can be obtained by commanding a value of 0xff (255) to any channel volume register or the master volume register. when volume offsets are provided via the master volume register, any channel wh ose total volume is le ss than -91 db will be muted. all changes in volume take place at zero-crossings when zce = 1 (configuration register h) on a per - channel basis as this creates the smoothest possible volume d7 d6 d5 d4 d3 d2 d1 d0 c4m c4vbp c4vt4 c4vt3 c4vt2 c4vt1 c4vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c5m c5vbp c5vt4 c5vt3 c5vt2 c5vt1 c5vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c6m c6vbp c6vt4 c6vt3 c6vt2 c6vt1 c6vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c7m c7vbp c7vt4 c7vt3 c7vt2 c7vt1 c7vt0 00010000 d7 d6 d5 d4 d3 d2 d1 d0 c8m c8vbp c8vt4 c8vt3 c8vt2 c8vt1 c8vt0 00010000
registers STA321MP 32/50 doc id 022647 rev 1 transitions. when zce = 0, volume updates occur immediately. each channel also contains an individual channel volume bypass. if a pa rticular channel has volume bypassed via the cnvbp = 1 register, then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. each channel also contains a channel mute. if cnm = 1 a soft mute is performed on that channel. mv[7:0] volume offset from channel value 0x00 0 db 0x01 -0.5 db 0x02 -1 db ?? 0x4c -38 db ?? 0xfe -127 db 0xff hardware channel mute cnv[7:0] volume 0x00 +48 db 0x01 +47.5 db 0x02 +47 db ?? 0x5f +0.5 db 0x60 0 db 0x61 -0.5 db ?? 0xfe -79.5 db 0xff hardware channel mute cnvt[4:0] volume 0x00 to 0x06 +10 db 0x07 +9 db ?? 0x0f +1 db 0x10 0 db 0x11 -1 db ?? 0x19 -9 db 0x1a to 0x1f -10 db
STA321MP registers doc id 022647 rev 1 33/50 7.2.26 channel input m apping channels 1 and 2 (0x1b) 7.2.27 channel input m apping channels 3 and 4 (0x1c) 7.2.28 channel input m apping channels 5 and 6 (0x1d) 7.2.29 channel input m apping channels 7 and 8 (0x1e) each channel received via i 2 s can be mapped to any internal processing channel via the channel input mapping re gisters. this allows for flexibilit y in processing, simplifies output stage designs, and enab les the ability to perform crossovers . the default settings of these registers map each i 2 s input channel to its corresponding processing channel. d7 d6 d5 d4 d3 d2 d1 d0 c2im2 c2im1 c2im0 c1im2 c1im1 c1im0 001 000 d7 d6 d5 d4 d3 d2 d1 d0 c4im2 c4im1 c4im0 c3im2 c3im1 c3im0 011 010 d7 d6 d5 d4 d3 d2 d1 d0 c6im2 c6im1 c6im0 c5im2 c5im1 c5im0 101 100 d7 d6 d5 d4 d3 d2 d1 d0 c8im2 c8m1 c8im0 c7im2 c7im1 c7im0 111 110 cnim[2:0] seria l input from 000 channel 1 001 channel 2 010 channel 3 011 channel 4 100 channel 5 101 channel 6 110 channel 7 111 channel 8
registers STA321MP 34/50 doc id 022647 rev 1 7.2.30 biquad internal channel loop-through (0x28) each internal processing channel can receive tw o possible inputs at the input to the biquad block. the input can come either from the output of that channel?s mix#1 engine or from the output of the bass/treble (biquad #10) of the previous channel. in this scenario, channel 1 receives channel 8. this enables the use of more than 10 biquads on any given channel at the loss of the number of separate internal processing channels. d7 d6 d5 d4 d3 d2 d1 d0 c8blp c7blp c6blp c5blp c4blp c3blp c2blp c1blp 00000000 bit rw rst name description 7:0 rw 0 cnblp for n = 1 to 8: 0: input from channel n mix#1 engine output - normal operation 1: input from channel (n - 1) biquad #10 output - loop operation
STA321MP registers doc id 022647 rev 1 35/50 7.2.31 mix internal ch annel loop-through (0x29) each internal processing channel can receive two possible sets of inputs at the inputs to the mix#1 block. the inputs can come from the outputs of the interpolation block as normally occurs (cnmxlp = 0) or they can come from the outputs of the mix#2 block. this enables the use of additional filtering after the second mix block at the expense of losing this processing capability on the channel. 7.2.32 eq bypass (0x2a) eq control can be bypassed on a per-channel basis. if eq control is bypassed on a given channel the prescale and all 10 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel. 7.2.33 tone contro l bypass (0x2b) tone control (bass/treble) can be bypassed on a per-channel basis. if tone control is bypassed on a given channel the two filters that tone control utilizes are made available as user programmable biquads #9 and #10. d7 d6 d5 d4 d3 d2 d1 d0 c8mxlp c7mxlp c6mxlp c5mxlp c4mxlp c3mxlp c2mxlp c1mxlp 00000000 bit rw rst name description 7:0 rw 0 cnmxlp for n = 1 to 8: 0: inputs to channel n mix #1 engine from interpolation outputs - normal operation 1: inputs to channel n mix #1 engine from mix#2 engine outputs - loop operation d7 d6 d5 d4 d3 d2 d1 d0 c8eqbp c7eqbp c6eqbp c5eqbp c4eqcbp c3eqbp c2eqbp c1eqbp 00000000 bit rw rst name description 7:0 rw 0 cneqbp for n = 1 to 8: 0: perform eq on channel n - normal operation 1: bypass eq on channel n d7 d6 d5 d4 d3 d2 d1 d0 c8tcb c7tcb c6tcb c5tcb c4tcb c3tcb c2tcb c1tcb 00000000
registers STA321MP 36/50 doc id 022647 rev 1 7.2.34 tone control (0x2c) this is the tone control boost / cut as a function of the btc and ttc bits. 7.2.35 channel 1 and 2 output timing (0x33) 7.2.36 channel 3 and 4 output timing (0x34) 7.2.37 channel 5 and 6 output timing (0x35) d7 d6 d5 d4 d3 d2 d1 d0 ttc3 ttc2 ttc1 ttc0 btc3 btc2 btc1 btc0 01110111 btc[3:0] / ttc[3:0) boost / cut 0000 -12 db 0001 -12 db ?? 0111 -4 db 0110 -2 db 0111 0 db 1000 +2 db 1001 +4 db ?? 1101 +12 db 1110 +12 db 1111 +12db d7 d6 d5 d4 d3 d2 d1 d0 c2ot2 c2ot1 c2ot0 c1ot2 c1ot1 c1ot0 100 000 d7 d6 d5 d4 d3 d2 d1 d0 c4ot2 c4ot1 c4ot0 c3ot2 c3ot1 c3ot0 110 010 d7 d6 d5 d4 d3 d2 d1 d0 c6ot2 c6ot1 c6ot0 c5ot2 c5ot1 c5ot0 101 001
STA321MP registers doc id 022647 rev 1 37/50 7.2.38 channel 7 and 8 output timing (0x36) the centering of the individual channel pwm output periods can be adjusted by the output timing registers. pwm slot settings can be chosen to ensure that pulse transitions do not occur at the same time on different channels using the same power device. there are 8 possible settings, the appropriate setting varies based on the application and connections to the ffx power devices. 7.2.39 channel i 2 s output mapping ch annels 1 and 2 (0x37) 7.2.40 channel i 2 s output mapping ch annels 3 and 4 (0x38) 7.2.41 channel i 2 s output mapping ch annels 5 and 6 (0x39) d7 d6 d5 d4 d3 d2 d1 d0 c8ot2 c8ot1 c8ot0 c7ot2 c7ot1 c7ot0 111 011 cnot[2:0] pwm slot 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 d7 d6 d5 d4 d3 d2 d1 d0 c2om2 c2om1 c2om0 c1om2 c1om1 c1om0 001 000 d7 d6 d5 d4 d3 d2 d1 d0 c4om2 c4om1 c4om0 c3om2 c3om1 c3om0 011 010 d7 d6 d5 d4 d3 d2 d1 d0 c6om2 c6om1 c6om0 c5om2 c5om1 c5om0 101 100
registers STA321MP 38/50 doc id 022647 rev 1 7.2.42 channel i 2 s output mapping ch annels 7 and 8 (0x3a) each i 2 s output channel can receive data from any channel output of the volume block. which channel a particular i 2 s output receives is dependent upon that channel?s cnom register bits. 7.2.43 coefficient addr ess register 1 (0x3b) 7.2.44 coefficient addr ess register 2 (0x3c) 7.2.45 coefficient b1 data register, bits 23:16 (0x3d) d7 d6 d5 d4 d3 d2 d1 d0 c8om2 c8m1 c8om0 c7om2 c7om1 c7om0 111 110 cnom[2:0] serial output from 000 channel 1 001 channel 2 010 channel 3 011 channel 4 100 channel 5 101 channel 6 110 channel 7 111 channel 8 d7 d6 d5 d4 d3 d2 d1 d0 cfa9 cfa8 00 d7 d6 d5 d4 d3 d2 d1 d0 cfa7 cfa6 cfa5 cfa4 cfa3 cfa2 cfa1 cfa0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000
STA321MP registers doc id 022647 rev 1 39/50 7.2.46 coefficient b1 data register, bits 15:8 (0x3e) 7.2.47 coefficient b1 data register, bits 7:0 (0x3f) 7.2.48 coefficient b2 data register, bits 23:16 (0x40) 7.2.49 coefficient b2 data register, bits 15:8 (0x41) 7.2.50 coefficient b2 data register, bits 7:0 (0x42) 7.2.51 coefficient a1 data register, bits 23:16 (0x43) 7.2.52 coefficient a1 data register, bits 15:8 (0x44) d7 d6 d5 d4 d3 d2 d1 d0 c1b15 c1b14 c1b13 c1b12 c1b11 c1b10 c1b9 c1b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b7 c1b6 c1b5 c1b4 c1b3 c1b2 c1b1 c1b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b23 c2b22 c2b21 c2b20 c2b19 c2b18 c2b17 c2b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b15 c2b14 c2b13 c2b12 c2b11 c2b10 c2b9 c2b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c2b7 c2b6 c2b5 c2b4 c2b3 c2b2 c2b1 c2b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c1b23 c1b22 c1b21 c1b20 c1b19 c1b18 c1b17 c1b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c3b15 c3b14 c3b13 c3b12 c3b11 c3b10 c3b9 c3b8 00000000
registers STA321MP 40/50 doc id 022647 rev 1 7.2.53 coefficient a1 data register, bits 7:0 (0x45) 7.2.54 coefficient a2 data register, bits 23:16 (0x46) 7.2.55 coefficient a2 data register, bits 15:8 (0x47) 7.2.56 coefficient a2 data register, bits 7:0 (0x48) 7.2.57 coefficient b0 data register, bits 23:16 (0x49) 7.2.58 coefficient b0 data register, bits 15:8 (0x4a) 7.2.59 coefficient b0 data register, bits 7:0 (0x4b) d7 d6 d5 d4 d3 d2 d1 d0 c3b7 c3b6 c3b5 c3b4 c3b3 c3b2 c3b1 c3b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b23 c4b22 c4b21 c4b20 c4b19 c4b18 c4b17 c4b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b15 c4b14 c4b13 c4b12 c4b11 c4b10 c4b9 c4b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c4b7 c4b6 c4b5 c4b4 c4b3 c4b2 c4b1 c4b0 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b23 c5b22 c5b21 c5b20 c5b19 c5b18 c5b17 c5b16 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b15 c5b14 c5b13 c5b12 c5b11 c5b10 c5b9 c5b8 00000000 d7 d6 d5 d4 d3 d2 d1 d0 c5b7 c5b6 c5b5 c5b4 c5b3 c5b2 c5b1 c5b0 00000000
STA321MP registers doc id 022647 rev 1 41/50 7.2.60 coefficient write control register (0x4c) coefficients for eq and bass management are handled internally in the STA321MP via ram. access to this ram is available to the user via an i 2 c register interface. a collection of i 2 c registers are dedicated to this func tion. one contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write of the coefficient(s) to ram. the following are instructions for re ading and writing coefficients. 7.3 reading a coefficient from ram 1. write the top 2 bits of the address to i 2 c register 0x3b 2. write the bottom 8 bits of the address to i 2 c register 0x3c 3. read the top 8 bits of the coefficient from i 2 c address 0x3d 4. read the middle 8 bits of the coefficient from i 2 c address 0x3e 5. read the bottom 8 bits of the coefficient from i 2 c address 0x3f 7.4 reading a set of coefficients from ram 1. write the top 2 bits of the address to i 2 c register 0x3b 2. write the bottom 8 bits of the address to i 2 c register 0x3c 3. read the top 8 bits of the coefficient from i 2 c address 0x3d 4. read the middle 8 bits of the coefficient from i 2 c address 0x3e 5. read the bottom 8 bits of the coefficient from i 2 c address 0x3f 6. read the top 8 bits of coefficient b2 from i 2 c address 0x40 7. read the middle 8 bits of coefficient b2 from i 2 c address 0x41 8. read the bottom 8 bits of coefficient b2 from i 2 c address 0x42 9. read the top 8 bits of coefficient a1 from i 2 c address 0x43 10. read the middle 8 bits of coefficient a1 from i 2 c address 0x44 11. read the bottom 8 bits of coefficient a1 from i 2 c address 0x45 12. read the top 8 bits of coefficient a2 from i 2 c address 0x46 13. read the middle 8 bits of coefficient a2 from i 2 c address 0x47 14. read the bottom 8 bits of coefficient a2 from i 2 c address 0x48 15. read the top 8 bits of coefficient b0 from i 2 c address 0x49 16. read the middle 8 bits of coefficient b0 from i 2 c address 0x4a 17. read the bottom 8 bits of coefficient b0 from i 2 c address 0x4b d7 d6 d5 d4 d3 d2 d1 d0 wa w1 00
registers STA321MP 42/50 doc id 022647 rev 1 7.5 writing a single coefficient to ram 1. write the top 2 bits of the address to i 2 c register 0x3b 2. write the bottom 8 bits of the address to i 2 c register 0x3c 3. write the top 8 bits of the coefficient in i 2 c address 0x3d 4. write the middle 8 bits of the coefficient in i 2 c address 0x3e 5. write the bottom 8 bits of the coefficient in i 2 c address 0x3f 6. write 1 to the w1 bit in i 2 c address 0x4c 7.6 writing a set of coefficients to ram 1. write the top 2 bits of the starting address to i 2 c register 0x3b 2. write the bottom 8 bits of the starting address to i 2 c register 0x3c 3. write the top 8 bits of coefficient b1 in i 2 c address 0x3d 4. write the middle 8 bits of coefficient b1 in i 2 c address 0x3e 5. write the bottom 8 bits of coefficient b1 in i 2 c address 0x3f 6. write the top 8 bits of coefficient b2 in i 2 c address 0x40 7. write the middle 8 bits of coefficient b2 in i 2 c address 0x41 8. write the bottom 8 bits of coefficient b2 in i 2 c address 0x42 9. write the top 8 bits of coefficient a1 in i 2 c address 0x43 10. write the middle 8 bits of coefficient a1 in i 2 c address 0x44 11. write the bottom 8 bits of coefficient a1 in i 2 c address 0x45 12. write the top 8 bits of coefficient a2 in i 2 c address 0x46 13. write the middle 8 bits of coefficient a2 in i 2 c address 0x47 14. write the bottom 8 bits of coefficient a2 in i 2 c address 0x48 15. write the top 8 bits of coefficient b0 in i 2 c address 0x49 16. write the middle 8 bits of coefficient b0 in i 2 c address 0x4a 17. write the bottom 8 bits of coefficient b0 in i 2 c address 0x4b 18. write 1 to the wa bit in i 2 c address 0x4c the mechanism for writing a set of coefficients to ram provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. when using this technique, the 10-bit address specifies the address of the biquad b1 coefficient (for example, decimals 0, 5, 10, 15, ?, 100, ? 395) , and the STA321MP will generate the ram addresses as offsets from this base value to write the complete set of coefficient data.
STA321MP equalization and mixing doc id 022647 rev 1 43/50 8 equalization and mixing figure 8. channel mixer 8.1 post-scale the STA321MP provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. this is a 24-bit signed fractional multiply. the scale factor for this multiply is loaded into ram using the same i 2 c registers as the biquad coefficients and the bass-management. this post-scale factor can be used in conjunc tion with an adc-equipped microcontroller to perform power-supply error correction. all channels can use channel 1 by setting the post- scale link bit. channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 cxmix1 cxmix2 cxmix3 cxmix4 cxmix5 cxmix6 cxmix7 cxmix8 channel x am045 333 v1 table 10. ram block for biquads, mixing, and bass management index (decimal) index (hex) coefficient default 0 0x00 channel 1 - biquad 1 c1h10 (b1/2) 0x000000 1 0x01 c1h11 (b2) 0x000000 2 0x02 c1h12 (a1/2) 0x000000 3 0x03 c1h13 (a2) 0x000000 4 0x04 c1h14 (b0/2) 0x400000 5 0x05 channel 1 - biquad 2 c1h20 0x000000
equalization and mixing STA321MP 44/50 doc id 022647 rev 1 ??? ? ? 49 0x31 channel 1 - biquad 10 c1ha4 0x400000 50 0x32 channel 2 - biquad 1 c2h10 0x000000 51 0x33 c2h11 0x000000 ??? ? ? 99 0x63 channel 2 - biquad 10 c2ha4 0x4000000 100 0x64 channel 3 - biquad 1 c3h10 0x000000 ??? ? ? 399 0x18f channel 8 - biquad 10 c8ha4 0x400000 400 0x190 channel 1 - pre-scale c1pres 0x7fffff 401 0x191 channel 2 - pre-scale c2pres 0x7fffff 402 0x192 channel 3 - pre-scale c3pres 0x7fffff ??? ? ? 407 0x197 channel 8 - pre-scale c8pres 0x7fffff 408 0x198 channel 1 - post-scale c1psts 0x7fffff 409 0x199 channel 2 - post-scale c2psts 0x7fffff ??? ? ? 415 0x19f channel 8 - post-scale c8psts 0x7fffff 416 0x1a0 channel 1 - mix#1 1 c1mx11 0x7fffff 417 0x1a1 channel 1 - mix#1 2 c1mx12 0x000000 ??? ? ? 423 0x1a7 channel 1 - mix#1 8 c1mx18 0x000000 424 0x1a8 channel 2 - mix#1 1 c2mx11 0x000000 425 0x1a9 channel 2 - mix#1 2 c2mx12 0x7fffff ??? ? ? 463 0x1cf channel 8 - mix#1 8 c8mx18 0x7fffff 464 0x1d0 channel 1 - mix#2 1 c1mx21 0x7fffff 465 0x1d1 channel 1 - mix#2 2 c1mx22 0x000000 ??? ? ? 471 0x1d7 channel 1 - mix#2 8 c1mx28 0x000000 472 0x1d8 channel 2 - mix#2 1 c2mx21 0x000000 473 0x1d9 channel 2 - mix#2 2 c2mx22 0x7fffff ??? ? ? 527 0x20f channel 8 - mix#2 8 c8mx28 0x7fffff table 10. ram block for biquads, mixing, and bass management (continued) index (decimal) index (hex) coefficient default
STA321MP equalization and mixing doc id 022647 rev 1 45/50 8.2 variable max power correction 8.2.1 mpcc1-2 (0x4d, 0x4e) the mpcc bits determine the 16 msbs of the mpc compensation coefficient. this coefficient is used in place of the default coefficient when mpcv = 1. 8.3 variable distortion compensation 8.3.1 dcc1-2 (0x4f, 0x50) the dcc bits determine the 16 msbs of the distortion compensation coefficient. this coefficient is used in place of th e default coefficient when dccv = 1. 8.4 reserved registers address: (0x01) address: (0x03) address: (0x51, 0x52) address(0x53) d7 d6 d5 d4 d3 d2 d1 d0 mpcc15 mpcc14 mpcc13 mpcc12 mpcc11 mpcc10 mpcc9 mpcc8 00101101 d7 d6 d5 d4 d3 d2 d1 d0 mpcc7 mpcc6 mpcc5 mpcc4 mpcc3 mpcc2 mpcc1 mpcc0 11000000 d7 d6 d5 d4 d3 d2 d1 d0 dcc15 dcc14 dcc13 dcc12 dcc11 dcc10 dcc9 dcc8 11110011 d7 d6 d5 d4 d3 d2 d1 d0 dcc7 dcc6 dcc5 dcc4 dcc3 dcc2 dcc1 dcc0 00110011
package information STA321MP 46/50 doc id 022647 rev 1 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 9.1 tqfp64 package figure 9. tqfp64 (10 x 10 x 1.4 mm) mechanical data and package dimensions outline and mechanical data a a2 a1 b c 16 17 3 2 33 4 8 49 64 e 3 d 3 e1 e d1 d e 1 k b tqfp64 l l1 s e a ting pl a ne 0.0 8 mm dim. mm inch min. typ. max. min. typ. max. a 1.60 0.06 3 a1 0.05 0.15 0.002 0.006 a2 1. 3 5 1.40 1.45 0.05 3 0.055 0.057 b 0.17 0.22 0.27 0.0066 0.00 8 6 0.0106 c 0.09 0.00 3 5 d11. 8 0 12.00 12.20 0.464 0.472 0.4 8 0 d1 9. 8 0 10.00 10.20 0. 38 60. 3 94 0.401 d 3 7.50 0.295 e 0.50 0.0197 e11. 8 0 12.00 12.20 0.464 0.472 0.4 8 0 e1 9. 8 0 10.00 10.20 0. 38 60. 3 94 0.401 e 3 7.50 0.295 l 0.45 0.60 0.75 0.0177 0.02 3 6 0.0295 l1 1.00 0.0 3 9 3 k 0? (min.), 3 .5? (min.), 7?(m a x.) ccc 0.0 8 00.00 3 1 tqfp64 (10 x 10 x 1.4mm) 00514 3 4 e ccc
STA321MP package information doc id 022647 rev 1 47/50 9.2 vfqfpn56 package figure 10. vfqfpn56 (8 x 8 x 0.9 mm) package mechanical outline 8 26 8 201_b
package information STA321MP 48/50 doc id 022647 rev 1 table 11. vfqfpn56 (8 x 8 x 0.9 mm) package dimensions reference mm min. typ. max. a 0.80 0.90 1.00 a1 0 0.05 d8.00 d2 refer to the exposed pad variations in ta b l e 1 2 e8.00 e2 refer to the exposed pad variations in ta b l e 1 2 b 0.25 0.30 0.35 b1 0.20 0.25 0.30 e (pad pitch) (1) 1. refer to figure 10 on page 47 l1 0.05 0.15 aaa 0.15 bbb 0.10 ddd 0.05 eee 0.08 fff 0.10 ccc 0.10 table 12. exposed pad variations variation d2 e2 min. typ. max. min. typ. max. a 5.85 5.90 5.95 5.85 5.90 5.95 b 4.25 4.30 4.35 4.25 4.30 4.35
STA321MP revision history doc id 022647 rev 1 49/50 10 revision history table 13. document revision history date revision changes 07-feb-2012 1 initial release.
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